25/3D Level Heterogeneous Integration • Heterogeneous Integration • In the context of describing 25D/3D packaging level of technology • Integrating dissimilar chips using a packaging technology with I/O density higher than organic substrate (Feature size smaller than organic substrate, or 3D die) • Technology drivers • High bandwidth This integration scheme is called 25D TSV Additionally, silicon layers can be stacked tiertotier on top of each other, which reduces the physical area allocated for each component This tiertotier stacking is called 3D TSV technology In the dynamic random access memory (DRAM) space, 3D TSV has been deployed in both highbandwidth memory 2D vs 25D vs 3D ICs 101 By Max Maxfield 6 I see a lot of articles bouncing around the Internet these days about 25D and 3D ICs One really good one that came out recently was 25D ICs are more than a stepping stone to 3D ICs by Mike Santarini of Xilinx On the other hand, there are a lot of other articles that have "3D ICs
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